1. Field of the Invention
The present invention relates to a phase synchronization circuit.
2. Description of the Related Art
Recently, various electronic devices often use a phase synchronization circuit (hereinafter, PLL (Phase Locked Loop)) to generate output signal in synchronization with the phase of input signal. FIG. 5 depicts an example of an integrated PLL 300. A VCO (Voltage Controlled Oscillator) 400 outputs an output signal OUT having a frequency corresponding to a charging voltage of a capacitor C. If the phase of the output signal OUT is delayed from the phase of the input signal IN, a phase comparison circuit 410 outputs a high-level (hereinafter, H-level) pulse signal QA for a period corresponding to a phase difference. If the phase of the output signal OUT is advanced from the phase of the input signal IN, the phase comparison circuit 410 outputs an H-level pulse signal QB for a period corresponding to a phase difference. A charge pump 420 is a circuit that charges/discharges the capacitor C depending on the pulse signals QA, QB and if the H-level pulse signal QA is input to the charge pump 420, a switch SW1 is turned on and the capacitor C connected through a terminal 430 is charged with a bias current of a current source I1. On the other hand, the H-level pulse signal QB is input to the charge pump 420, a switch SW2 is turned on and the capacitor C is discharged with a bias current of a current source I2. A resistor R makes up a low-pass filter with the capacitor C to attenuate the high-frequency component of the charging/discharging current of the charge pump 420 and compensate the phase of the feedback loop in the PLL 300. The bias current value of the current source I1 is determined based on a set value of a bias current adjustment circuit 440 and the frequency of the output signal OUT of the VCO 400 is increased as the charging voltage of the capacitor C is increased. Therefore, the PLL 300 having the configuration of FIG. 5 operates such that the phase of the output signal OUT conforms to the phase of the input signal IN.
The state of the output signal OUT and the input signal IN having the matched phase, i.e., the locked state of the PLL 300 will be described. Since the charging voltage of the capacitor C does not need to be changed when the PLL 300 is locked, the phase comparison circuit 410 may set the outputs of the pulse signals QA, QB to low. However, when the outputs of the pulse signals QA, QB are set to low, if the charging voltage of the capacitor C is reduced due to, for example, a leak current of the capacitor C and a slight phase difference is generated, the high-level pulse signal QA corresponding to the slight phase difference may not turn on the switch SW1 because of a parasitic capacitance, etc., of the switch SW1, resulting in a problem that the PLL 300 does not operate. Therefore, as exemplarily illustrated in FIG. 6, the phase comparison circuit 410 is driven to output the high-level pulse signals QA, QB such that the respective switches SW1, SW2 are turned on for the same periods so as not to change the charging voltage of the capacitor C if the PLL 300 is locked (see, e.g., Japanese Patent Application Laid-Open Publication No. 2002-111493 or 2002-368611).
Even when the PLL 300 is locked and the respective switches SW1, SW2 are turned on for the same periods by the high-level pulse signals QA, QB output from the phase comparison circuit 410, if respective bias current values of the current sources I1, I2 charging/discharging the capacitor C are different, the charging voltage of the capacitor C cannot be kept constant and, as a result, the PLL 300 cannot be kept locked. Even if the current sources I1, I2 are designed such that the respective bias current values are made identical, it is difficult to make the both bias current values identical because of production variations. Therefore, an arbitrary number of PLLs may be extracted as samples from, for example, a plurality of PLLs included in a wafer, and the bias current adjustment circuit 440 may be set such that the bias current value of the current source I1 becomes identical to the bias current value of the current source I2 in other PLLs included in the wafer based on the bias current values of the current sources I1, I2 of the extracted PLLs for typical integrated PLLs.
If the charging/discharging current values of the charge pumps in other PLLs included in the wafer are set in advance based on the current values of the charging/discharging currents of the charge pumps in the PLLs extracted as the sample from the wafer as described above, predicted charging/discharging current values are set for charge pumps of PLLs no extracted as the samples and, therefore, it is problematically difficult to accurately match the current values of the charging current and the discharging current.